This invention is directed to MOS-type image sensors, and more particularly to an arrangement for reading out data from such sensor arrays.
A conventional MOS-type image sensor may be arranged substantially as shown in FIG. 1. The image sensor includes a sensor array 10 comprising an array of MOS-type sensing elements, and a vertical shift register 12 for selectively energizing rows in the sensor array 10. The array 10 provides a plurality of outputs, with the plurality being assumed to be 768 for purposes of the following description. Each of the 768 outputs from the sensor array is connected to the source of a respective one of 768 video transfer transistors 14, and the drains of the transfer transistors 14 are connected to four output terminals 16. Thus, each output terminal is coupled to the drains of 192 transfer transistors. A horizontal shift register 18 clocked by a clock source (not shown) selectively energizes the gates of appropriate transfer transistors in order to couple the sensor array outputs to the output terminal 16.
The operation of the image sensor shown in FIG. 1 is known in the art and need not be described in detail at this time. However, such image sensors have typically exhibited excessive output capacitances at each of the four output terminals 16. These output capacitances determine the S/N ratio of the system output, and it would therefore be generally desirable to minimize the output capacitances of the output terminals 16 in order to increase the S/N ratio and thereby improve system performance.
It is therefore an object of the present invention to provide an image sensor having improved S/N output characteristics, and it is a more particular object of the present invention to improve the S/N output characteristics of an image sensor by reducing the output capacitances of the sensor output terminals.